1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device such as a DRAM (Dynamic Random Access Memory) having a calibration circuit for adjusting impedance of an output buffer included in an output circuit.
Priority is claimed on Japanese Patent Application No. 2009-013047, filed Jan. 23, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In a semiconductor device typically a DRAM, it is necessary to control distortion in a data transmission waveform caused due to reflection, wherein the control is made by adjusting impedance of a transmission system so as to perform high speed data transmission.
Such impedance adjustment is performed by adjusting impedance of an output buffer circuit using a so-called calibration circuit.
For example, Japanese Unexamined Patent Application, First Publication, No. 2008-48361 discloses a technique of adjusting impedance of an output buffer in a calibration period which is 64 times of an external clock cycle.